The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2015
Filed:
Mar. 11, 2013
Applicant:
Nanya Technology Corporation, Taoyuan, TW;
Inventors:
Chien-An Yu, Taipei, TW;
Yuan-Sung Chang, New Taipei, TW;
Yi-Fong Lin, New Taipei, TW;
Chin-Piao Chang, New Taipei, TW;
Chih-Huang Wu, Taoyuan County, TW;
Wen-Chieh Wang, Taoyuan County, TW;
Assignee:
NANYA TECHNOLOGY CORPORATION, Taoyuan, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66666 (2013.01); H01L 29/7827 (2013.01); H01L 27/10814 (2013.01); H01L 27/10873 (2013.01); H01L 27/10891 (2013.01);
Abstract
Provided is a method for fabricating a semiconductor device, which includes the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar, and a doped region is disposed at a bottom of each pillar. An insulation layer is formed below each doped region. In addition, a gate and a gate dielectric are formed on the sidewalls of each pillar.