The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2015

Filed:

Dec. 28, 2012
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

James A. McCall, Portland, OR (US);

Kuljit S. Bains, Olympia, WA (US);

Derek M. Conrow, Sherwood, OR (US);

Aaron Martin, El Dorado Hills, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/012 (2006.01); G06F 3/041 (2006.01); H03K 19/00 (2006.01); H03K 19/0175 (2006.01);
U.S. Cl.
CPC ...
G06F 3/041 (2013.01); H03K 19/0005 (2013.01); H03K 19/017545 (2013.01);
Abstract

An output driver includes control logic configured to switch on a pull-up circuit and a pull-down circuit to provide an output impedance for a logic low on a transmission line. The output driver includes a variable pull-up resistor. The control logic is configured to switch on the pull-up circuit to a first value of impedance to drive a logic high on the transmission line. The control logic is configured to switch on the pull-up circuit to a second value of impedance and to switch on the pull-down circuit to provide the output impedance to drive a logic low on the transmission line. The system could alternatively be configured for the inverse to switch on a combination of pull-up and pull-down circuits for a logic high, where the pull-down circuit is switched on for a logic low.


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