The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2015

Filed:

Feb. 19, 2015
Applicant:

Shinko Electric Industries Co., Ltd., Nagano, JP;

Inventors:

Noriyoshi Shimizu, Nagano, JP;

Hitoshi Sakaguchi, Nagano, JP;

Wataru Kaneda, Nagano, JP;

Masato Tanaka, Nagano, JP;

Akio Rokugawa, Nagano, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H01L 23/538 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); H05K 3/40 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0298 (2013.01); H01L 23/5383 (2013.01); H05K 1/0271 (2013.01); H05K 1/112 (2013.01); H05K 1/181 (2013.01); H05K 3/4644 (2013.01); H05K 3/4007 (2013.01); H05K 3/4602 (2013.01); H05K 2201/0195 (2013.01); H05K 2201/0367 (2013.01); H05K 2201/10674 (2013.01); H05K 2203/025 (2013.01);
Abstract

A wiring board includes first insulating layers and second insulating layers formed on a core layer in this order; a third insulating layer and a solder resist layer formed on another surface of the core layer in this order, first wiring layers and second wiring layers formed in the first insulating layers and the second insulating layers, respectively, wherein a first end surface of the first via wiring exposes from the first surface of the outermost first insulating layer to be directly connected with an outermost second wiring layer, the first via wiring and the outermost second wiring layer being separately formed, the first surface of the outermost first insulating layer and the first end surface of the first via wiring are polished surfaces, smooth surfaces and are flush with each other, and the wiring density of the second wiring layers is higher than that of the first wiring layers.


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