The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2015

Filed:

Oct. 31, 2011
Applicants:

Rohit Sunkam Ramanujam, Santa Clara, CA (US);

Sailesh Kumar, San Jose, CA (US);

William Lynch, Los Altos, CA (US);

Inventors:

Rohit Sunkam Ramanujam, Santa Clara, CA (US);

Sailesh Kumar, San Jose, CA (US);

William Lynch, Los Altos, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/28 (2006.01); H04L 12/42 (2006.01); G06F 15/78 (2006.01); H04L 12/40 (2006.01); H04J 1/16 (2006.01);
U.S. Cl.
CPC ...
H04L 12/42 (2013.01); G06F 15/7825 (2013.01); H04L 12/40189 (2013.01); Y02B 60/1207 (2013.01); Y02B 60/1225 (2013.01);
Abstract

An apparatus comprising a chip comprising a plurality of nodes, a first plurality of links connecting the plurality of nodes in a first ring network having a first topology, and a second plurality of links connecting the plurality of nodes in a second ring network having a second topology, wherein the first topology is different than the second topology.


Find Patent Forward Citations

Ramanujam, Rohit. (2015). Asymmetric ring topology for reduced latency in on-chip ring networks (U.S. Patent No. 9148298). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9148298

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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