The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2015

Filed:

Jul. 25, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Yueli Liu, Chandler, AZ (US);

Chong Zhang, Chandler, AZ (US);

Qinglei Zhang, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/48 (2006.01); H01L 21/50 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/48 (2013.01); H01L 21/50 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2224/13101 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/15192 (2013.01);
Abstract

Embodiments of the present disclosure are directed towards interconnect structures for embedded bridge in integrated circuit (IC) package assemblies. In one embodiment, a method includes depositing an electrically insulative layer on a bridge interconnect structure, the bridge interconnect structure including a die contact that is configured to route electrical signals between a first die and a second die, depositing a sacrificial layer on the electrically insulative layer, forming an opening through the sacrificial layer and the electrically insulative layer to expose the die contact and forming a die interconnect of the first die or the second die by depositing an electrically conductive material into the opening. Other embodiments may be described and/or claimed.


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