The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2015
Filed:
Dec. 10, 2013
Applicants:
Yong-hoon Kim, Suwon-si, KR;
Ji-chul Kim, Yongin-si, KR;
Seong-ho Shin, Hwaseong-si, KR;
In-ho Choi, Seoul, KR;
Inventors:
Yong-Hoon Kim, Suwon-si, KR;
Ji-Chul Kim, Yongin-si, KR;
Seong-Ho Shin, Hwaseong-si, KR;
In-Ho Choi, Seoul, KR;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/36 (2006.01); H01L 23/373 (2006.01); H01L 23/498 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 23/36 (2013.01); H01L 23/3677 (2013.01); H01L 23/373 (2013.01); H01L 23/3736 (2013.01); H01L 23/49816 (2013.01); H01L 25/105 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/14181 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16245 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73203 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/06589 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1094 (2013.01); H01L 2924/15151 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15331 (2013.01);
Abstract
A semiconductor package stack may include a lower semiconductor package and an upper semiconductor package stacked on a lower package board. The upper semiconductor package may include an upper semiconductor chip mounted on an upper package board with an opening configured to expose a lower surface of the upper semiconductor chip and a first heat slug disposed within the opening, contacting the lower surface of the upper semiconductor chip, and contacting an upper surface of a lower semiconductor chip.