The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2015
Filed:
Aug. 05, 2013
Applicant:
Kabushiki Kaisha Toshiba, Tokyo, JP;
Inventors:
Tsukasa Nakai, Hino, JP;
Masaki Kondo, Kawasaki, JP;
Hiroyoshi Tanimoto, Yokohama, JP;
Nobutoshi Aoki, Yokohama, JP;
Assignee:
KABUSHIKI KAISHA TOSHIBA, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 45/06 (2013.01); G11C 13/003 (2013.01); G11C 13/0004 (2013.01); H01L 27/2409 (2013.01); H01L 27/2481 (2013.01); H01L 45/12 (2013.01); H01L 45/126 (2013.01); H01L 45/144 (2013.01); G11C 2213/71 (2013.01); G11C 2213/72 (2013.01); G11C 2213/73 (2013.01); G11C 2213/74 (2013.01); G11C 2213/79 (2013.01);
Abstract
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell which stores data with two or more levels. The memory cell includes a structure includes a first electrode layer, a first semiconductor layer, a phase change film, an electrical insulating layer, a second semiconductor layer, and a second electrode layer arranged in order thereof, and the first semiconductor layer and the second semiconductor layer have carrier polarities different from each other.