The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2015
Filed:
Jan. 16, 2014
Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;
Stmicroelectronics SA, Montrouge, FR;
Bastien Giraud, Voreppe, FR;
Jean-Philippe Noel, Montbonnot Saint Martin, FR;
Maud Vinet, Rives sur Fure, FR;
Commissariat a l'energie atomique et aux energies alternatives, Paris, FR;
STMicroelectronics SA, Mountrouge, FR;
Abstract
An integrated circuit includes a silicon substrate, a ground plane above the substrate, a buried insulator layer above the ground plane, a silicon layer above the buried insulator layer and separated from the ground plane by the buried insulator layer, and an FDSOI transistor. The transistor has a channel adapted for being formed in the silicon layer, a source and drain in and/or on the silicon layer, and a gate covering an upper face of the channel and having a lateral portion covering a lateral face of the channel and above the ground plane. A distance between the lateral portion and the ground plane is not more than three nanometers and at least five times less than a thickness of the buried insulator layer between the ground plane and the silicon layer. The ground plane is separated from the gate by the buried insulator layer.