The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2015

Filed:

Jul. 16, 2013
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Ran Yan, Dresden, DE;

Nicolas Sassiat, Dresden, DE;

Jan Hoentschel, Dresden, DE;

Torben Balzer, Dresden, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 27/092 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 29/16 (2013.01); H01L 29/66477 (2013.01); H01L 29/78 (2013.01);
Abstract

In various aspects, methods of forming a semiconductor device and semiconductor devices are provided. In some illustrative embodiments herein, a silicon/germanium layer is provided on a semiconductor substrate. On the silicon/germanium layer, at least one insulating material layer is formed. After having performed a thermal annealing process, the at least one insulating material layer is removed in subsequent process sequences such that the silicon/germanium layer is at least partially exposed. In further processing sequences which are to be subsequently applied, a gate electrode is formed on the exposed silicon/germanium layer.


Find Patent Forward Citations

Loading…