The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2015

Filed:

Jul. 30, 2012
Applicants:

Martin Gerhardt, Dresden, DE;

Stefan Flachowsky, Dresden, DE;

Matthias Kessler, Dresden, DE;

Inventors:

Martin Gerhardt, Dresden, DE;

Stefan Flachowsky, Dresden, DE;

Matthias Kessler, Dresden, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2012.01); H01L 31/113 (2006.01); H01L 31/119 (2006.01); H01L 21/3205 (2006.01); H01L 21/4763 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82345 (2013.01); H01L 21/28202 (2013.01); H01L 21/823462 (2013.01); H01L 21/823842 (2013.01); H01L 21/823857 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 29/66545 (2013.01); H01L 29/7833 (2013.01);
Abstract

Method of forming transistor devices is disclosed that includes forming a first layer of high-k insulating material and a sacrificial protection layer above first and second active regions, removing the first layer of insulating material and the protection layer from above the second active region, removing the protection layer from above the first layer of insulating material positioned above the first active region, forming a second layer of high-k insulating material above the first layer of insulating material and the second active region, forming a layer of metal above the second layer of insulating material, and removing portions of the first and second layers of insulating material and the metal layer to form a first gate stack (comprised of the first and second layers of high-k material and the layer of metal) and a second gate stack (comprised of the second layer of high-k material and the layer of metal).


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