The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2015

Filed:

Oct. 02, 2013
Applicant:

Soitec, Bernin, FR;

Inventors:

Didier Landru, Champ Prés Froges, FR;

Fabrice Gritti, Voiron, FR;

Eric Guiot, Goncelin, FR;

Oleg Kononchuk, Grenoble, FR;

Christelle Veytizou, Bernin, FR;

Assignee:

SOITEC, Bernin, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/461 (2006.01); H01L 21/02 (2006.01); H01L 21/316 (2006.01); H01L 21/324 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02532 (2013.01); H01L 21/02238 (2013.01); H01L 21/02255 (2013.01); H01L 21/02422 (2013.01); H01L 21/31662 (2013.01); H01L 21/324 (2013.01); H01L 21/7624 (2013.01);
Abstract

A process for avoiding formation of an Si—SiO—Henvironment during a dissolution treatment of a semiconductor-on-insulator structure that includes a carrier substrate, an oxide layer, a thin layer of a semiconductor material and a peripheral ring in which the oxide layer is exposed. This process includes encapsulating at least the exposed oxide layer of the peripheral ring with semiconductor material by performing a creep thermal treatment; and performing an oxide dissolution treatment to reduce part of the thickness of the oxide layer. In this process, the semiconductor material that encapsulates the oxide layer has a thickness before the oxide dissolution that is at least twice that of the oxide that is to be dissolved, thus avoiding formation of an Si—SiO—Henvironment on the peripheral ring where the oxide layer would otherwise be exposed.


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