The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 2015
Filed:
Jan. 28, 2013
Sailesh Kumar, San Jose, CA (US);
Eric Norige, East Lansing, MI (US);
Joji Philip, San Jose, CA (US);
Mahmud Hassan, San Carlos, CA (US);
Sundari Mitra, Saratoga, CA (US);
Joseph Rowlands, San Jose, CA (US);
Sailesh Kumar, San Jose, CA (US);
Eric Norige, East Lansing, MI (US);
Joji Philip, San Jose, CA (US);
Mahmud Hassan, San Carlos, CA (US);
Sundari Mitra, Saratoga, CA (US);
Joseph Rowlands, San Jose, CA (US);
NetSpeed Systems, San Jose, CA (US);
Abstract
Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the number of layers needed in a NoC interconnect system based on the bandwidth requirements of the system traffic flows. The number of layers is dynamically allocated and minimized by performing load balancing of the traffic flows between the channels and routes of different NoC layers as they are mapped. Additional layers may be allocated to provide the additional virtual channels that may be needed for deadlock avoidance and to maintain the isolation properties between various system flows. Layer allocation for additional bandwidth and additional virtual channels (VCs) may be performed in tandem.