The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2015

Filed:

May. 07, 2014
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Hsing-Chih Liu, Taichung, TW;

Chia-Hao Yang, Zhubei, TW;

Ying-Chih Chen, Kaohsiung, TW;

Assignee:

MEDIATEK INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/538 (2006.01); H01L 23/528 (2006.01); H01L 23/50 (2006.01); H01L 23/495 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5221 (2013.01); H01L 23/49575 (2013.01); H01L 23/50 (2013.01); H01L 23/528 (2013.01); H01L 23/5381 (2013.01); H01L 23/5386 (2013.01);
Abstract

The invention provides a semiconductor package structure. The semiconductor package structure includes a base. A first die is mounted on the base. The first die comprises a plurality of first pads with a first pad area arranged in a first tier. A plurality of second pads with a second pad area is arranged in a second tier. A second die is mounted on the base. The second die comprises a plurality of third pads with the first pad area and a plurality of fourth pads with the second pad area alternately arranged in a third tier. A first bonding wire has two terminals respectively coupled to one of the first pads and one of the fourth pads. A second bonding wire has two terminals respectively coupled to one of the third pads and one of the second pads.


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