The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9129956 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 08, 2015

Filed:

Dec. 11, 2013
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hung-Jen Liao, Hsinchu, TW;

Jung-Hsuan Chen, Hsinchu, TW;

Chien Chi Tien, Hsinchu, TW;

Ching-Wei Wu, Caotun Town, TW;

Jui-Che Tsai, Tainan, TW;

Hong-Chen Cheng, Hsinchu, TW;

Chung-Hsing Wang, Baoshan Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 27/11 (2006.01); H01L 23/532 (2006.01); H01L 27/02 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49811 (2013.01); H01L 23/49827 (2013.01); H01L 23/528 (2013.01); H01L 23/53204 (2013.01); H01L 27/0203 (2013.01); H01L 27/11 (2013.01);
Abstract

An integrated circuit (IC) memory device that includes a first conductive layer, a second conductive layer electrically coupled to the first conductive layer, the second conductive layer formed over the first conductive layer, a third conductive layer separated from the second conductive layer, the third conductive layer formed over the second conductive layer, a fourth conductive layer electrically coupled to the third conductive layer, the fourth conductive layer formed over the third conductive layer, a 2P2E pin box formed in and electrically coupled to the first conductive layer or the second conductive layer and a 1P1E pin box formed in and electrically coupled to the third conductive layer or the fourth conductive layer.


Find Patent Forward Citations

Liao, Hung-Jen. (2015). Device having multiple-layer pins in memory mux1 layout (U.S. Patent No. 9129956). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9129956

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