The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2015

Filed:

Dec. 19, 2012
Applicant:

Invensas Corporation, San Jose, CA (US);

Inventors:

Cyprian Emeka Uzoh, San Jose, CA (US);

Pezhman Monadgemi, Fremont, CA (US);

Terrence Caskey, Santa Cruz, CA (US);

Fatima Lina Ayatollahi, Fremont, CA (US);

Belgacem Haba, Saratoga, CA (US);

Charles G. Woychik, San Jose, CA (US);

Michael Newman, Dublin, CA (US);

Assignee:

Invensas Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/36 (2006.01); H01L 23/367 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76829 (2013.01); H01L 23/36 (2013.01); H01L 23/481 (2013.01); H01L 21/76898 (2013.01); H01L 23/3677 (2013.01); H01L 2924/00 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method for making an interconnect element includes depositing a thermally conductive layer on an in-process unit. The in-process unit includes a semiconductor material layer defining a surface and edges surrounding the surface, a plurality of conductive elements, each conductive element having a first portion extending through the semiconductor material layer and a second portion extending from the surface of the semiconductor material layer. Dielectric coatings extend over at least the second portion of each conductive element. The thermally conductive layer is deposited on the in-process unit at a thickness of at least 10 microns so as to overlie a portion of the surface of the semiconductor material layer between the second portions of the conductive elements with the dielectric coatings positioned between the conductive elements and the thermally conductive layer.


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