The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2015
Filed:
Dec. 18, 2013
Qualcomm Incorporated, San Diego, CA (US);
Kambiz Samadi, San Diego, CA (US);
Shreepad Amar Panth, Atlanta, GA (US);
Pratyush Kamal, San Diego, CA (US);
Yang Du, Carlsbad, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
Placement of Monolithic Inter-tier Vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace is disclosed. In one embodiment, a method of placing MIVs in a monolithic 3DIC using clustering is provided. The method comprises determining if any MIV placement clusters are included within a plurality of initial MIV placements of a plurality of MIVs within an initial 3DIC layout plan. The method further comprises aligning each MIV of the plurality of MIVs within each MIV placement cluster in the initial 3DIC layout plan at a final MIV placement for each MIV placement cluster to provide a clustered 3DIC layout plan.