The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2015
Filed:
Jul. 12, 2013
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Chun-Hsien Lin, Hsinchu, TW;
Kuo-Hung Chao, Hsinchu, TW;
Yi-Ping Hsieh, Hsinchu, TW;
Yen-Di Tsen, Chung-Ho, TW;
Jui-Chun Peng, Hsinchu, TW;
Heng-Hsin Liu, New Taipei, TW;
Jong-I Mou, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
The present disclosure relates to a method of monitoring wafer topography. A position and orientation of a plurality first alignment shapes disposed on a surface of a wafer are measured. Wafer topography as a function of wafer position is modeled by subjecting the wafer to an alignment which simultaneously minimizes misalignment between the wafer and a patterning apparatus and maximizes a focus of radiation on the surface. A non-correctable error is determined as a difference between the modeled wafer topography and a measured wafer topography. A maximum non-correctable error per field is determined for a wafer, and a mean variation in the maximum non-correctable error across each field within each wafer of a lot is determined, both within a layer and across layers. These values are then verified against a set of statistical process control rules to determine if they are within a specification limit of the manufacturing process.