The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2015

Filed:

Jun. 20, 2012
Applicants:

Mahesh S. Natu, Sunnyvale, CA (US);

Anil S. Keshavamurthy, Portland, OR (US);

Alberto J. Munoz, Los Altos, CA (US);

Tessil Thomas, Bangalore, IN;

Inventors:

Mahesh S. Natu, Sunnyvale, CA (US);

Anil S. Keshavamurthy, Portland, OR (US);

Alberto J. Munoz, Los Altos, CA (US);

Tessil Thomas, Bangalore, IN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2006.01); G06F 11/34 (2006.01);
U.S. Cl.
CPC ...
G06F 11/3409 (2013.01); G06F 9/45558 (2013.01); G06F 2009/45591 (2013.01); G06F 2201/815 (2013.01); G06F 2201/885 (2013.01);
Abstract

Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for tracking per-virtual machine ('VM') resource usage independent of a virtual machine monitor ('VMM'). In various embodiments, a first logic unit may associate one or more virtual central processing units (“vCPUs”) operated by one or more physical processing units of a computing device with a first VM of a plurality of VMs operated by the computing device, and collect data about resources used by the one or more physical processing units to operate the one or more vCPUs associated with the first VM. In various embodiments, a second logic unit of the computing device may determine resource-usage by the first VM based on the collected data. In various embodiments, the first and second logic units may perform these functions independent of a VMM of the computing device.


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