The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 25, 2015
Filed:
Oct. 17, 2014
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Assignee:
UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/06 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01); H01L 21/28 (2006.01); H01L 27/115 (2006.01); H01L 21/266 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66825 (2013.01); H01L 21/266 (2013.01); H01L 21/28273 (2013.01); H01L 27/11521 (2013.01); H01L 29/42324 (2013.01); H01L 29/42328 (2013.01); H01L 29/42332 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/7881 (2013.01); H01L 29/7882 (2013.01);
Abstract
A method of fabricating a semiconductor device is disclosed. The method includes the steps of: sequentially forming agate dielectric layer and a first gate layer on a semiconductor substrate, wherein the gate dielectric layer is between the first gate layer and the semiconductor substrate; forming at least an opening in the first gate layer; forming a first dielectric layer conformally on the semiconductor substrate wherein the first dielectric layer covers the first gate layer; and forming a second gate layer filling the opening and overlapping the first gate layer.