The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2015

Filed:

Jan. 29, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;

Inventors:

Bo-Jr Huang, Tainan, TW;

Nan-Hsin Tseng, Tainan, TW;

Ping-Han Tsai, New Taipei, TW;

Wei-Hao Kao, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8242 (2006.01); H01L 49/02 (2006.01); H01L 23/522 (2006.01); H01L 27/02 (2006.01); H01L 27/06 (2006.01); H01L 21/768 (2006.01); H01L 27/08 (2006.01);
U.S. Cl.
CPC ...
H01L 28/40 (2013.01); H01L 21/768 (2013.01); H01L 23/5226 (2013.01); H01L 27/0207 (2013.01); H01L 27/0688 (2013.01); H01L 27/0805 (2013.01);
Abstract

A semiconductor arrangement and methods of forming the same are described. A semiconductor arrangement includes a first tier including a first capacitor, a second tier over the first tier, the second tier including a second capacitor, and a first substrate between the first tier and the second tier. The first capacitor is connected to the second capacitor through the substrate. A plurality of tiers are contemplated, such that a total capacitance of the semiconductor arrangement increases based upon interconnection of metal layers of different tiers. Additionally, the semiconductor arrangement has a greater area efficiency as compared to multiple capacitors in parallel.


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