The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2015

Filed:

Dec. 26, 2013
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Dongjiang Wang, Shanghai, CN;

Danny Huang, Shanghai, CN;

Steven Zhang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); H01L 21/76816 (2013.01); H01L 21/76895 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Local interconnect structures and fabrication methods are provided. A dielectric layer can be formed on a semiconductor substrate. A first film layer can be patterned on the dielectric layer to define a region surrounded by a local interconnect structure to be formed. A sidewall spacer can be formed and patterned surrounding the first film layer on an exposed surface portion of the dielectric layer. A second film layer can be formed on the exposed surface portion of the dielectric layer and can have a top surface substantially flushed with a top surface of the sidewall spacer. The patterned sidewall spacer can be removed to form a first opening. After forming the first opening, the dielectric layer can be etched to form a second opening through the dielectric layer. The second opening can be filled with a conductive material to form the local interconnect structure.


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