The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2015

Filed:

Dec. 12, 2012
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventors:

Chunlong Li, Beijing, CN;

Junfeng Li, Beijing, CN;

Jiang Yan, Newburgh, NY (US);

Chao Zhao, Kessel-lo, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/338 (2006.01); H01L 21/28 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28123 (2013.01); H01L 29/513 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon, and trimming the hard mask layer so that the trimmed hard mask layer has a width less than or equal to 22 nm; and etching the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed hard mask layer, and removing the hard mask layer and the top-layer amorphous silicon.


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