The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 18, 2015
Filed:
Apr. 16, 2014
Assembly structure for connecting multiple dies into a system-in-package chip and the method thereof
Tsung Chuan Whang, Cupertino, CA (US);
Yi-chieh Wang, Taiching, TW;
Tsung Chuan Whang, Cupertino, CA (US);
Yi-Chieh Wang, Taiching, TW;
Gloval Unichip Corp., Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Abstract
The present invention discloses an efficient way to connect multiple integrated circuit dies using redistribution layers (RDL) for making wire connections. Antenna diodes are used to create ground paths so as to remove non-sticking pads on the RDL to ensure the integrity of the wire connections before packaging the multiple integrated circuit dies into a system-in-package (SIP) chip, thereby eliminating unnecessary yield loss in a functional test caused by the non-sticking pads. In another aspect, electrostatic discharge (ESD) protection can be provided through the antenna diodes across two different power domains by disposing a diode in one integrated circuit die for ESD protection of a terminal in another integrated circuit die.