The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2015

Filed:

Sep. 04, 2013
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Zhendong Hong, San Jose, CA (US);

Susie Tzeng, Fremont, CA (US);

Amol Joshi, Sunnyvale, CA (US);

Ashish Bodke, San Jose, CA (US);

Divya Pisharoty, Fremont, CA (US);

Usha Raghuram, Saratoga, CA (US);

Olov Karlsson, San Jose, CA (US);

Kisik Choi, Hopewell Junction, NY (US);

Salil Mujumdar, San Jose, CA (US);

Paul R. Besser, Sunnyvale, CA (US);

Jinping Liu, Ballston Lake, NY (US);

Hoon Kim, Guilderland, NY (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 27/092 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 21/28097 (2013.01); H01L 21/28185 (2013.01); H01L 21/28194 (2013.01); H01L 21/823835 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01);
Abstract

One method for forming replacement gate structures for NMOS and PMOS transistors includes performing an etching process to remove a sacrificial gate structure for the NMOS and PMOS transistors to thereby define NMOS and PMOS gate cavities, depositing a gate insulation layer in the gate cavities, depositing a first metal layer on the gate insulation layer in the gate cavities, performing at least one process operation to form (1) an NMOS metal silicide material above the first metal layer within the NMOS gate cavity, the NMOS metal silicide material having a first amount of atomic silicon, and (2) a PMOS metal silicide material above the first metal layer within the PMOS gate cavity, the PMOS metal silicide material having a second amount of atomic silicon, and wherein the first and second amounts of atomic silicon are different, and forming gate cap layers within the NMOS and PMOS gate cavities.


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