The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 2015
Filed:
Jan. 10, 2014
International Business Machines Corporation, Armonk, NY (US);
Charles J. Alpert, Austin, TX (US);
Mark D. Aubel, Essex Junction, VT (US);
Gregory F. Ford, San Jose, CA (US);
Zhuo Li, Cedar Park, TX (US);
Chin Ngai Sze, Austin, TX (US);
Paul G. Villarrubia, Austin, TX (US);
Natarajan Viswanathan, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Boundary timing in the design of an integrated circuit is facilitated by designating a subset of boundary latches in the circuit, and applying placement constraints to the boundary latches. Global placement is performed while maintaining the boundary latch placement constraints, and a timing driven placement is performed after implementing timing assertions. Boundary latches are designated using a depth-first search to identify the first latches along interconnection paths with the PI/PO, and filtering out ineligible latches according to designer rules. A latch can be filtered out if it is in a large cluster of latches driven by a primary input or driving a primary output, if it drives too many POs, or is a feed-through latch. Constraints include movebounds, preplacement, or attractive forces between boundary latches and other boundary fixed objects, i.e., a fixed gate or a PI/PO.