The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2015

Filed:

Mar. 15, 2013
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Thaddeus C. McCracken, Portland, OR (US);

Joseph P. Jarosz, Sunnyvale, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01);
Abstract

Disclosed are methods, systems, and articles of manufactures for implementing a physical design with force directed placement or floorplanning and layout decomposition by identifying multiple nodes and then iteratively generating multiple cells by using the multiple nodes in a decomposition process and applying force model(s) to iteratively morph the cells until convergence criteria are satisfied to generate a layout or floorplan of an electronic design without requiring complete conductivity for the electronic design. The initially identified custom conductivity information is maintained throughout this iterative process.


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