The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2015

Filed:

Oct. 30, 2013
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Inventors:

Hiroshi Uozaki, Kanagawa, JP;

Yasuhiro Takeda, Kanagawa, JP;

Keiichi Maekawa, Kanagawa, JP;

Takumi Hasegawa, Kanagawa, JP;

Kota Funayama, Kanagawa, JP;

Yoshiki Maruyama, Kanagawa, JP;

Kazutoshi Shiba, Kanagawa, JP;

Shuichi Kudo, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 27/11 (2006.01); H01L 21/28 (2006.01); H01L 27/105 (2006.01); H01L 27/115 (2006.01); H01L 29/423 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 29/788 (2013.01); H01L 21/28282 (2013.01); H01L 27/105 (2013.01); H01L 27/1104 (2013.01); H01L 27/11573 (2013.01); H01L 29/42344 (2013.01); H01L 29/792 (2013.01);
Abstract

An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers.


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