The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2015

Filed:

Feb. 28, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ching-Yu Chai, Hsinchu, TW;

Chin-Sheng Chen, Taoyuan, TW;

Wei-Yi Hu, Zhubei, TW;

Jui-Feng Kuan, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5068 (2013.01); G06F 17/5081 (2013.01);
Abstract

A system for designing an integrated circuit generates a schematic of the integrated circuit based on a set of system design rule constraints. The system also receives a proposed device array layout from a device array design module. The device array design module is configured to generate the proposed device array layout free from the set of system design rule constraints. The system further generates a revised schematic of the integrated circuit including the proposed device array layout. The system additionally determines if the revised schematic violates one or more of the system design rule constraints.


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