The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2015

Filed:

Dec. 11, 2013
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Han-Wen Liao, Taichung, TW;

Wei-Tai Lin, Taichung, TW;

Wen-Sheng Wang, Taichung, TW;

Chih-Yu Lin, Tainan, TW;

Cherng-Chang Tsuei, Hsin-Chu, TW;

Chen-Hsiang Lu, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/308 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3088 (2013.01); H01L 21/3086 (2013.01);
Abstract

A method for etching a target layer of a semiconductor device in an etching apparatus is provided. To form an element, the method includes forming a photoresist pattern on the target layer of the semiconductor device, in which the photoresist pattern has an after-develop-inspection critical dimension (ADI CD). A target after-etch-inspection critical dimension (AEI CD) of the element is provided, as well as a trim time of the target layer. The etching apparatus is provided and a formation time of a protective layer on an inner wall of the etching apparatus is determined based on the ADI CD, the target AEI CD and the trim time. The protective layer for the predetermined formation time is formed to perform a trimming process on the target layer for the trim time by using the photoresist pattern as a mask, so as to form the element.


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