The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2015

Filed:

Mar. 12, 2012
Applicants:

Jun Furuichi, Nagano, JP;

Akihiko Tateiwa, Nagano, JP;

Naoyuki Koizumi, Nagano, JP;

Inventors:

Jun Furuichi, Nagano, JP;

Akihiko Tateiwa, Nagano, JP;

Naoyuki Koizumi, Nagano, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 3/30 (2006.01); H05K 3/46 (2006.01); H01L 21/48 (2006.01); H05K 3/20 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4682 (2013.01); Y10T 29/49139 (2015.01); H01L 2224/16225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81193 (2013.01); H01L 2924/09701 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/19105 (2013.01); H05K 3/205 (2013.01); H05K 2201/10378 (2013.01); H01L 2924/01019 (2013.01); H01L 2924/01068 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 21/4857 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2224/814 (2013.01); H01L 2224/81801 (2013.01); H01L 2924/15153 (2013.01); H01L 2224/131 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/07802 (2013.01);
Abstract

A wiring substrate includes a structure in which a plurality of wiring layers are stacked through insulating layers intervening therebetween, and which has a first surface side and a second surface side, the first surface side where a semiconductor element is to be mounted, the second surface side being located at an opposite side to the first surface side, an interposer buried in an outermost one of the insulating layers located at the first surface side, and electrically connected to the semiconductor element to be mounted, and a sheet-shaped member buried in an outermost one of the insulating layers located at the second surface side, wherein, the interposer and the sheet-shaped member are disposed at symmetrical positions symmetrical each other.


Find Patent Forward Citations

Loading…