The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2015
Filed:
Apr. 08, 2014
Wei-sheng Lei, San Jose, CA (US);
Prabhat Kumar, Fremont, CA (US);
James S. Papanu, San Rafael, CA (US);
Ajay Kumar, Cupertino, CA (US);
Brad Eaton, Menlo Park, CA (US);
Wei-Sheng Lei, San Jose, CA (US);
Prabhat Kumar, Fremont, CA (US);
James S. Papanu, San Rafael, CA (US);
Ajay Kumar, Cupertino, CA (US);
Brad Eaton, Menlo Park, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The method also involves patterning the mask with a laser scribing process to provide gaps in the mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the gaps in the mask to singulate the integrated circuits. The method also involves, subsequent to plasma etching the semiconductor wafer, removing etch residue from sidewalls of the singulated integrated circuits.