The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2015
Filed:
May. 15, 2013
Applicant:
Hitachi Power Semiconductor Device, Ltd., Hitachi-shi, Ibaraki, JP;
Inventors:
Yukihiro Kumagai, Hitachinaka, JP;
Michiaki Hiyoshi, Yokohama, JP;
Assignee:
Hitachi Power Semiconductor Device, Ltd., Hitachi-shi, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/488 (2006.01); H01L 21/02 (2006.01); H01L 23/373 (2006.01); H01L 23/544 (2006.01); H01L 25/07 (2006.01); H01L 23/047 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/488 (2013.01); H01L 21/02107 (2013.01); H01L 23/047 (2013.01); H01L 23/3735 (2013.01); H01L 23/544 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 25/072 (2013.01); H01L 2223/54406 (2013.01); H01L 2223/54413 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/54433 (2013.01); H01L 2224/26175 (2013.01); H01L 2224/291 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/83447 (2013.01); H01L 2224/83455 (2013.01); H01L 2224/83815 (2013.01); H01L 2924/3512 (2013.01); H01L 2924/13055 (2013.01); H01L 2223/54486 (2013.01); H01L 23/498 (2013.01); H01L 23/49844 (2013.01); H01L 2924/1305 (2013.01);
Abstract
In a semiconductor device where a metal circuit layer is disposed over a main planar surface of an insulating substrate, a semiconductor chip is connected by way of a solder over the metal circuit layer, and a metal wiring is connected over the metal circuit layer, in which a solder flow prevention area comprising a linear oxide material is formed between the semiconductor chip and the ultrasonic metal bonding region over the metal circuit layer.