The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2015

Filed:

Jan. 27, 2014
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Ching-Lin Chan, Hsinchu, TW;

Cheng-Chi Lin, Hsinchu, TW;

Shih-Chin Lien, Hsinchu, TW;

Shyi-Yuan Wu, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/739 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7823 (2013.01); H01L 29/7393 (2013.01); H01L 29/0649 (2013.01); H01L 29/0619 (2013.01); H01L 29/0869 (2013.01); H01L 29/66681 (2013.01); H01L 29/66325 (2013.01);
Abstract

Provided is a semiconductor device including a substrate, an isolation structure, a gate structure, source and drain regions and a conductive layer. The source and drain regions are disposed in the substrate. The isolation structure is disposed between the source and drain regions. The gate structure is disposed on the substrate between the source and drain regions. The conductive layer is disposed on the substrate, extends from above the source region to above the isolation structure and is electrically connected to the source region. The substrate has first and second areas. The source region in the second area has a border curvature greater than that in the first area. The width of the portion of the conductive layer covering the isolation structure in the second area has a width greater than that in the first area.


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