The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2015

Filed:

Aug. 16, 2013
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsin-Chu, TW;

Inventors:

Chen-Liang Chu, Hsin-Chu, TW;

Fei-Yuh Chen, Hsinchu, TW;

Chih-Wen Yao, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3205 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/00 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42376 (2013.01); H01L 29/0653 (2013.01); H01L 29/4238 (2013.01); H01L 29/66659 (2013.01); H01L 29/7835 (2013.01);
Abstract

The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.


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