The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2015

Filed:

Sep. 26, 2012
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventor:

Bogdan M. Simion, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); B29C 37/00 (2006.01); B29C 43/28 (2006.01); H01L 25/10 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
B29C 37/0075 (2013.01); B29C 43/28 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/1088 (2013.01); H01L 21/565 (2013.01); H01L 21/566 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 24/97 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 25/18 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/92125 (2013.01); H01L 2224/97 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15321 (2013.01); H01L 2924/15331 (2013.01); H01L 2924/18161 (2013.01); H01L 23/49811 (2013.01); H01L 23/49833 (2013.01);
Abstract

Embodiments of the present disclosure are directed towards a mold chase for integrated circuit package assembly and associated techniques and configurations. In one embodiment, a method includes receiving a package substrate, the package substrate including a first die mounted on the package substrate by a plurality of first interconnect structures, and a plurality of second interconnect structures disposed on the package substrate and configured to route electrical signals of a second die, protecting a top surface of individual interconnect structures of the plurality of second interconnect structures from deposition of a mold material, and depositing the mold material on the package substrate between the individual interconnect structures of the plurality of second interconnect structures. Other embodiments may be described and/or claimed.


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