The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2015

Filed:

Aug. 04, 2010
Applicants:

John Roberts, Ottawa, CA;

Ahmad Mizan, Ottawa, CA;

Girvan Patterson, Ottawa, CA;

Greg Klowak, Ottawa, CA;

Inventors:

John Roberts, Ottawa, CA;

Ahmad Mizan, Ottawa, CA;

Girvan Patterson, Ottawa, CA;

Greg Klowak, Ottawa, CA;

Assignee:

GAN SYSTEMS INC., Ottawa, ON, CA;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7787 (2013.01); H01L 29/1075 (2013.01); H01L 29/2003 (2013.01); H01L 29/4175 (2013.01); H01L 29/41758 (2013.01); H01L 29/42316 (2013.01);
Abstract

A gallium nitride (GaN) device that has greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The layout scheme, which uses island electrodes rather than finger electrodes, is shown to increase the active area density over that of conventional interdigitated structures. Ultra low on resistance transistors can be built using the island topology. Specifically, the present invention, which uses conventional GaN lateral technology and electrode spacing, provides a means to enhance cost/effective performance of all lateral GaN structures.


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