The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2015
Filed:
Jul. 17, 2013
Bi-o Kim, Seoul, KR;
Toshiro Nakanishi, Seongnam-si, KR;
Jin-tae Noh, Suwon-si, KR;
Chang-woo Sun, Hwaseong-si, KR;
Seung-hyun Lim, Seoul, KR;
Jae-young Ahn, Seongnam-si, KR;
Ki-hyun Hwang, Seongnam-si, KR;
Bi-O Kim, Seoul, KR;
Toshiro Nakanishi, Seongnam-si, KR;
Jin-Tae Noh, Suwon-si, KR;
Chang-Woo Sun, Hwaseong-si, KR;
Seung-Hyun Lim, Seoul, KR;
Jae-Young Ahn, Seongnam-si, KR;
Ki-Hyun Hwang, Seongnam-si, KR;
Abstract
Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer.