The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2015

Filed:

Apr. 19, 2012
Applicants:

Shivani Srivastava, Boise, ID (US);

Kunal Shrotri, Boise, ID (US);

Fawad Ahmed, Boise, ID (US);

Inventors:

Shivani Srivastava, Boise, ID (US);

Kunal Shrotri, Boise, ID (US);

Fawad Ahmed, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/469 (2006.01); H01L 21/02 (2006.01); H01L 27/108 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02164 (2013.01); H01L 21/02318 (2013.01); H01L 27/10876 (2013.01); H01L 27/10891 (2013.01); H01L 21/28185 (2013.01); H01L 21/28211 (2013.01);
Abstract

Some embodiments include methods of forming silicon dioxide in which silicon dioxide is formed across silicon utilizing a first treatment temperature of no greater than about 1000° C., and in which an interface between the silicon dioxide and the silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. Some embodiments include methods of forming transistors in which a trench is formed to extend into monocrystalline silicon. Silicon dioxide is formed along multiple crystallographic planes along an interior of the trench utilizing a first treatment temperature of no greater than about 1000° C., and an interface between the silicon dioxide and the monocrystalline silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. A transistor gate is formed within the trench, and a pair of source/drain regions is formed within the monocrystalline silicon adjacent the transistor gate. Some embodiments include DRAM cells.


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