The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Nov. 05, 2008
Applicants:

Hai Ding, Phoenix, AZ (US);

Fuchao Wang, Plano, TX (US);

Zhiyong Xie, The Colony, TX (US);

Inventors:

Hai Ding, Phoenix, AZ (US);

Fuchao Wang, Plano, TX (US);

Zhiyong Xie, The Colony, TX (US);

Assignee:

STMicroelectronics, Inc., Coppell, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/82 (2006.01); H01L 23/525 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5258 (2013.01); H01L 27/10894 (2013.01); Y02E 60/12 (2013.01); H01L 23/5256 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Methods of fabricating a multi-layer semiconductor structure are provided. In one embodiment, a method includes depositing a first dielectric layer over a semiconductor structure, depositing a first metal layer over the first dielectric layer, patterning the first metal layer to form a plurality of first metal lines, and depositing a second dielectric layer over the first metal lines and the first dielectric layer. The method also includes removing a portion of the second dielectric layer over selected first metal lines to expose a respective top surface of each of the selected first metal lines. The method further includes reducing a thickness of the selected first metal lines to be less than a thickness of the unselected first metal lines. A multi-layer semiconductor structure is also provided.


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