The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Mar. 29, 2012
Applicants:

Sundar Iyer, Palo Alto, CA (US);

Shang-tse Chuang, Los Altos, CA (US);

Thu Nguyen, Palo Alto, CA (US);

Sanjeev Joshi, San Jose, CA (US);

Adam Kablanian, Los Altos Hills, CA (US);

Inventors:

Sundar Iyer, Palo Alto, CA (US);

Shang-Tse Chuang, Los Altos, CA (US);

Thu Nguyen, Palo Alto, CA (US);

Sanjeev Joshi, San Jose, CA (US);

Adam Kablanian, Los Altos Hills, CA (US);

Assignee:

Memoir Systems, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 7/10 (2006.01); G11C 8/16 (2006.01); G11C 11/413 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1075 (2013.01); G11C 8/16 (2013.01); G11C 7/10 (2013.01); G11C 11/413 (2013.01);
Abstract

Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.


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