The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 2015
Filed:
Jun. 27, 2014
Intermolecular Inc., San Jose, CA (US);
Kabushiki Kaisha Toshiba, Tokyo, JP;
Sandisk 3d Llc, Milpitas, CA (US);
Yun Wang, San Jose, CA (US);
Tony P. Chiang, Campbell, CA (US);
Imran Hashim, Saratoga, CA (US);
Tim Minvielle, San Jose, CA (US);
Dipankar Pramanik, Saratoga, CA (US);
Takeshi Yamaguchi, Kanagawa, JP;
Intermolecular, Inc., San Jose, CA (US);
Kabushiki Kaisha Toshiba, Tokyo, JP;
SanDisk 3D LLC, Milpitas, CA (US);
Abstract
Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from alloys of transition metals. Some examples of such alloys include chromium containing alloys that may also include nickel, aluminum, and/or silicon. Other examples include tantalum and/or titanium containing alloys that may also include a combination of silicon and carbon or a combination of aluminum and nitrogen. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature processing. In some embodiments, the breakdown voltage of a current limiting layer is at least about 8V. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layers while maintaining their performance.