The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2015

Filed:

Jan. 31, 2014
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Kazutaka Miyano, Tokyo, JP;

Ryuji Takishita, Tokyo, JP;

Takeshi Konno, Tokyo, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B 19/00 (2006.01); G11C 7/22 (2006.01); H03L 7/081 (2006.01); G11C 7/10 (2006.01); G11C 11/406 (2006.01); G11C 11/4074 (2006.01); G11C 11/4096 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); H03L 7/0814 (2013.01); H03L 7/0816 (2013.01); H03L 7/0818 (2013.01); G11C 7/1039 (2013.01); G11C 11/40611 (2013.01); G11C 11/4074 (2013.01); G11C 11/4096 (2013.01); G11C 2207/2227 (2013.01);
Abstract

A semiconductor device includes a first input terminal configured to receive a first clock signal, first control terminals configured to receive first control signals respectively, an output terminal, first inverters each including an input node coupled to the first input terminal, a control node coupled to a corresponding one of the first control terminals and an output node coupled to the output terminal, each of the first inverters being configured to be controlled to output an inverted first clock signal to the output terminal in response to a corresponding one of the first control signals supplied to a corresponding one of the control nodes, and an additional first inverter including an input node coupled to the first input terminal and an output node coupled to the output terminal, the additional first inverter being free from any other control nodes to output an inverted first clock signal to the output terminal.


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