The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2015

Filed:

Sep. 04, 2013
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yang-Hung Chang, Taipei, TW;

Kai-Hsiung Chen, New Taipei, TW;

Chih-Ming Ke, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G03F 9/00 (2006.01); G03F 1/00 (2012.01); G21K 5/00 (2006.01); G01R 31/26 (2014.01); G01L 21/00 (2006.01); G01P 21/00 (2006.01); G01N 37/00 (2006.01); H01L 21/00 (2006.01); G06F 19/00 (2011.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); H01L 21/00 (2013.01); G06F 2217/06 (2013.01); G06F 19/00 (2013.01); G06F 2217/02 (2013.01); G06F 2217/16 (2013.01); G03F 9/00 (2013.01); G06F 2217/12 (2013.01); G21K 5/00 (2013.01); G03F 1/00 (2013.01); G01R 31/26 (2013.01); G01P 21/00 (2013.01); G01N 37/00 (2013.01);
Abstract

A method for overlay monitoring and control is introduced in the present disclosure. The method comprises forming resist patterns on one or more wafers in a lot by an exposing tool; selecting a group of patterned wafers in the lot using a wafer selection model; selecting a group of fields for each of the selected group of patterned wafers using a field selection model; selecting at least one point in each of the selected group of fields using a point selection model; measuring overlay errors of the selected at least one point on a selected wafer; forming an overlay correction map using the measured overlay errors on the selected wafer; and generating a combined overlay correction map using the overlay correction map of each selected wafer in the lot.


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