The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2015
Filed:
Jun. 13, 2013
Mohammad Kamruzzaman Chowdhury, Santa Clara, CA (US);
Wei-sheng Lei, San Jose, CA (US);
Todd Egan, Fremont, CA (US);
Brad Eaton, Menlo Park, CA (US);
Madhava Rao Yalamanchili, Morgan Hill, CA (US);
Ajay Kumar, Cupertino, CA (US);
Mohammad Kamruzzaman Chowdhury, Santa Clara, CA (US);
Wei-Sheng Lei, San Jose, CA (US);
Todd Egan, Fremont, CA (US);
Brad Eaton, Menlo Park, CA (US);
Madhava Rao Yalamanchili, Morgan Hill, CA (US);
Ajay Kumar, Cupertino, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
Uniform masking for wafer dicing using laser and plasma etch is described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits having bumps or pillars includes uniformly spinning on a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile