The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 2015
Filed:
Feb. 10, 2011
Land grid array package capable of decreasing a height difference between a land and a solder resist
Applicants:
Hee-chul Lee, Hwaseong-si, KR;
Myung-kee Chung, Cheonan-si, KR;
Kun-dae Yeom, Cheonan-si, KR;
Inventors:
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Suwon-Si, Gyeonggi-Do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3121 (2013.01); H01L 2924/15313 (2013.01); H01L 2224/09517 (2013.01); H01L 2224/33517 (2013.01); H01L 23/49811 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 24/48 (2013.01); Y10S 438/948 (2013.01);
Abstract
A land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a connection portion connecting the semiconductor chip and the substrate, and a support layer formed on part of a surface of a first land.