The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2015

Filed:

Apr. 02, 2013
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Ralf Otremba, Kaufbeuren, DE;

Josef Höglauer, Heimstetten, DE;

Klaus Schiess, Allensbach, DE;

Chooi Mei Chong, Melaka, MY;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/051 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49524 (2013.01); H01L 23/051 (2013.01); H01L 23/3107 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/73265 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 24/48 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/13091 (2013.01); H01L 2224/73221 (2013.01); H01L 2224/73263 (2013.01); H01L 2224/40245 (2013.01); H01L 24/33 (2013.01); H01L 24/40 (2013.01); H01L 24/41 (2013.01); H01L 2924/13062 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/13055 (2013.01);
Abstract

A semiconductor package includes a semiconductor die having a first electrode at a first side and a second electrode at a second side opposing the first side, a first lead under the semiconductor die and connected to the first electrode at a first level of the package, and a second lead having a height greater than the first lead and terminating at a second level in the package above the first level, the second level corresponding to a height of the semiconductor die. A connector of a single continuous planar construction over the semiconductor die and the second lead is connected to both the second electrode and the second lead at the same second level of the package.


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