The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 2015
Filed:
May. 07, 2012
Desmond J. Donegan, Jr., Poughkeepsie, NY (US);
Abhishek Dube, Belmont, CA (US);
Steven Jones, Balton Spa, NY (US);
Jophy S. Koshy, Wappingers Falls, NY (US);
Viorel Ontalus, Danbury, CT (US);
Desmond J. Donegan, Jr., Poughkeepsie, NY (US);
Abhishek Dube, Belmont, CA (US);
Steven Jones, Balton Spa, NY (US);
Jophy S. Koshy, Wappingers Falls, NY (US);
Viorel Ontalus, Danbury, CT (US);
International Business Machines Corporation, Armonk, NY (US);
GlobalFoundries, Inc., Grand Cayman, KY;
Abstract
A method of forming transistors with close proximity stressors to channel regions of the transistors is provided. The method includes forming a first transistor, in a first region of a substrate, having a gate stack on top of the first region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the first region including a source and drain region of the first transistor; forming a second transistor, in a second region of the substrate, having a gate stack on top of the second region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the second region including a source and drain region of the second transistor; covering the first transistor with a photo-resist mask without covering the second transistor; creating recesses in the source and drain regions of the second transistor; and forming stressors in the recesses.