The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2015

Filed:

Dec. 27, 2013
Applicant:

Maxim Integrated Products, Inc., San Jose, CA (US);

Inventors:

Xuejun Ying, San Jose, CA (US);

Li Li, Fremont, CA (US);

Amit S. Kelkar, Flower Mound, TX (US);

Brian S. Poarch, Frisco, TX (US);

Assignee:

Maxim Integrated Products, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B81C 1/00 (2006.01); B81B 7/00 (2006.01);
U.S. Cl.
CPC ...
B81C 1/00626 (2013.01); B81B 7/0009 (2013.01);
Abstract

A device includes sidewalls formed in a wafer surface, where the sidewalls descend to a recessed surface. The recessed surface generally promotes resist coverage on the wafer surface, including corners (e.g., junctions between the wafer surface and various surface topographies, such as cavities, the recessed surface, and so forth) on the wafer. In one or more implementations, a wet etching procedure is used to form the sidewalls and recessed surface. A resist material (e.g., a photoresist material) is deposited onto the wafer surface, where the photoresist fully covers one or more of the top corners of the wafer surface. In one or more implementations, the recessed surface is positioned adjacent a trench formed in the wafer to promote resist coverage on the top surface of the wafer.


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