The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2015

Filed:

Sep. 11, 2013
Applicant:

Globalfoundries, Inc., Grand Cayman, KY (US);

Inventors:

Xiang Hu, Clifton Park, NY (US);

Jin Ping Liu, Ballston Lake, NY (US);

Jill Hildreth, Slingerlands, NY (US);

Taejoon Han, Clifton Park, NY (US);

Assignee:

GLOBALFOUNDRIES, INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/02 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823431 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure overlying a semiconductor substrate. The fin structure defines a fin axis extending in a longitudinal direction perpendicular to a lateral direction and has two fin sidewalls parallel to the fin axis. The method includes forming gate structures overlying the fin structure and transverse to the fin axis. Further, the method includes growing an epitaxial material on the fin structure and confining growth of the epitaxial material in the lateral direction.


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