The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2015

Filed:

Jul. 07, 2010
Applicants:

Francis Ko, Taichung, TW;

Tzu-yu Wang, Taipei, TW;

Kewei Zuo, Yonghe, TW;

Henry Lo, Hsin-Chu, TW;

Jean Wang, Hsin-Chu, TW;

Chih-wei Lai, Hsin-Chu, TW;

Inventors:

Francis Ko, Taichung, TW;

Tzu-yu Wang, Taipei, TW;

Kewei Zuo, Yonghe, TW;

Henry Lo, Hsin-Chu, TW;

Jean Wang, Hsin-Chu, TW;

Chih-Wei Lai, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 19/00 (2011.01); H01L 21/00 (2006.01); G05B 17/02 (2006.01);
U.S. Cl.
CPC ...
G05B 17/02 (2013.01);
Abstract

A first embodiment is a method for semiconductor process control comprising clustering processing tools of a processing stage into a tool cluster based on processing data and forming a prediction model for processing a semiconductor wafer based on the tool cluster. A second embodiment is a method for semiconductor process control comprising providing cluster routes between first stage tool clusters and second stage tool clusters, assigning a comparative optimization ranking to each cluster route, and scheduling processing of wafers. The comparative optimization ranking identifies comparatively which cluster routes provide for high wafer processing uniformity. Further, wafers that require high wafer processing uniformity are scheduled to be processed along one cluster route that has a high comparative optimization ranking that identifies the one cluster route to have a highest wafer processing uniformity, and wafers that do not require high wafer processing uniformity are scheduled to be processed along another cluster route.


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